1. Field of the Invention
The invention relates generally to a semiconductor device and a method of fabricating same. More particularly, this invention relates to a semiconductor device having a buried gate line and a method of fabricating same.
This application claims priority to Korean Patent Application No. 10-2006-0097267, filed Oct. 2, 2006, the contents of which are hereby incorporated herein by reference in its entirety.
2. Description of Related Art
Semiconductor devices widely employ a discrete device such as a field effect transistor as a switching device. In the transistor, the operating speed of the switching device is significantly determined by the on current flowing through a channel between the source and drain regions. In general, a planar-type transistor may be formed by fabricating a gate electrode and the source and drain regions in a device-forming region of a substrate, i.e., an active region. Common planar-type transistors have a planar channel between the source and drain regions. The on-current of the planar-type transistor is proportional to the width of the active region, and inversely proportional to the distance between the source region and the drain region, i.e., a gate length. Thus, in order to increase the on-current and thus the operating speed of the device, the gate length has to be reduced, and the width of the active region has to be increased. However, the increase in the width of the active region in the planar-type transistor is contrary to the trend of reducing the size of highly integrated devices. Also, in the planar-type transistor, as the distance between the source and drain regions becomes short, a short channel effect may occur. Accordingly, because a conventional planar-type transistor contains a flat channel on the surface of the semiconductor substrate and is a planar-type channel device; it is structurally disadvantageous to downsize the device, without also incurring the short channel effect.
A transistor having a recess channel has been disclosed to overcome the short channel effect for a downsized transistor. The recess channel transistor contains a depressed channel region and an insulated gate electrode. The insulated gate electrode is disposed in the depressed channel region, i.e., a recess channel region. Accordingly, the recess channel transistor may ensure a relatively greater effective channel length than the planar-type transistor. That is, the recess channel transistor provides a structure capable of overcoming problems caused by the short channel effect. However, the recess channel transistor has another problem that makes subsequent processes such as formation of a contact plug and planarization difficult when the gate electrode is disposed to project upward from the semiconductor substrate. Also, an upper corner part of the depressed channel region may result in leakage current from a field crowding effect. Further, a highly difficult patterning process is required to form the projected gate electrode.
Another approach using a buried word line is disclosed in U.S. Pat. No. 6,770,535 B2 entitled “Semiconductor Integrated Circuit Device and Process for Manufacturing the Same” by Yamada et al. According to Yamada et al., a trench is formed across a channel region and an isolation layer. A word line filling a part of the trench is then formed. An insulating pattern filling the rest of the trench is formed thereafter. As a result, the world line is buried under the surface of the semiconductor substrate. The buried word line provides a relatively greater effective channel length. However, the effective channel width of the semiconductor device is determined by the channel region and the buried word line. Accordingly, this semiconductor device has substantially the same effective channel width as a planar-type MOS transistor. Consequently, the buried word line semiconductor device has a relatively lower current drivability than the planar-type MOS transistor. Also, the recess channel MOS transistor has a relatively adverse body effect as well as a difficult structure as compared to the planar-type MOS transistor.
Therefore, there is a need in the semiconductor arts for a semiconductor device capable of substantially overcoming the deficiencies described above and a method of fabrication, thereof.